ATmega640/1280/1281/2560/2561
24 2-wire Serial Interface .......................................................................... 241
24.1
24.2
24.3
24.4
24.5
24.6
24.7
24.8
24.9
Features ........................................................................................................241
2-wire Serial Interface Bus Definition ............................................................241
Data Transfer and Frame Format ..................................................................242
Multi-master Bus Systems, Arbitration and Synchronization .........................245
Overview of the TWI Module .........................................................................246
Using the TWI ................................................................................................249
Transmission Modes .....................................................................................252
Multi-master Systems and Arbitration ............................................................265
Register Description ......................................................................................266
25 AC – Analog Comparator .................................................................... 271
25.1
25.2
Analog Comparator Multiplexed Input ...........................................................271
Register Description ......................................................................................272
26 ADC – Analog to Digital Converter ..................................................... 275
26.1
26.2
26.3
26.4
26.5
26.6
26.7
26.8
Features ........................................................................................................275
Operation .......................................................................................................276
Starting a Conversion ....................................................................................277
Prescaling and Conversion Timing ................................................................278
Changing Channel or Reference Selection ...................................................282
ADC Noise Canceler .....................................................................................283
ADC Conversion Result .................................................................................288
Register Description ......................................................................................290
27 JTAG Interface and On-chip Debug System ...................................... 297
27.1
27.2
27.3
27.4
27.5
27.6
27.7
27.8
27.9
Features ........................................................................................................297
Overview ........................................................................................................297
TAP - Test Access Port .................................................................................298
Using the Boundary-scan Chain ....................................................................300
Using the On-chip Debug System .................................................................300
On-chip Debug Specific JTAG Instructions ...................................................301
Using the JTAG Programming Capabilities ...................................................302
Bibliography ...................................................................................................302
On-chip Debug Related Register in I/O Memory ...........................................302
28 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 303
28.1
28.2
Features ........................................................................................................303
System Overview ...........................................................................................303
v
2549L–AVR–08/07
ATMEL [ ATMEL ]
