Timing symbols refer to Figure 31-6.
Table 31-5. 2-wire Serial Bus Requirements
Symbol Parameter
Condition
Min
-0.5
Max
0.3 VCC
VCC + 0.5
–
Units
VIL
Input Low-voltage
V
V
V
V
VIH
Vhys
Input High-voltage
0.7 VCC
(1)
(1)
(2)
Hysteresis of Schmitt Trigger Inputs
Output Low-voltage
0.05 VCC
0
VOL
tr(1)
3 mA sink current
0.4
20 +
Rise Time for both SDA and SCL
300
ns
ns
(3)(2)
0.1Cb
20 +
tof
Output Fall Time from VIHmin to VILmax
10 pF < Cb < 400 pF(3)
0.1VCC < Vi < 0.9VCC
250
(1)
(3)(2)
0.1Cb
0
tSP
Ii
Ci(1)
Spikes Suppressed by Input Filter
Input Current each I/O Pin
50(2)
10
ns
µA
pF
(1)
-10
–
Capacitance for each I/O Pin
10
fCK(4) > max(16fSCL
250kHz)(5)
,
fSCL
SCL Clock Frequency
Value of Pull-up resistor
0
400
kHz
Ω
VCC – 0,4V
----------------------------
3mA
fSCL ≤ 100 kHz
1000ns
-------------------
Cb
Rp
VCC – 0,4V
----------------------------
3mA
f
SCL > 100 kHz
300ns
---------------
Ω
Cb
fSCL ≤ 100 kHz
SCL > 100 kHz
4.0
0.6
4.7
1.3
4.0
0.6
4.7
0.6
0
–
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
tHD;STA
Hold Time (repeated) START Condition
Low Period of the SCL Clock
High period of the SCL clock
Set-up time for a repeated START condition
Data hold time
f
–
fSCL ≤ 100 kHz(6)
fSCL > 100 kHz(7)
fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
–
tLOW
–
–
tHIGH
–
–
tSU;STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
f
SCL > 100 kHz
–
fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
3.45
0.9
–
0
250
100
4.0
0.6
4.7
1.3
Data setup time
–
–
Setup time for STOP condition
f
SCL > 100 kHz
fSCL ≤ 100 kHz
SCL > 100 kHz
–
–
Bus free time between a STOP and START
condition
f
–
Notes: 1. In ATmega640/1280/1281/2560/2561, this parameter is characterized and not 100% tested.
2. Required only for fSCL > 100 kHz.
3. Cb = capacitance of one bus line in pF.
4. fCK = CPU clock frequency
376
ATmega640/1280/1281/2560/2561
2549L–AVR–08/07
ATMEL [ ATMEL ]
