Figure 27-1. Block Diagram
I/O PORT 0
DEVICE BOUNDARY
BOUNDARY SCAN CHAIN
TDI
TDO
TCK
TMS
JTAG PROGRAMMING
INTERFACE
TAP
CONTROLLER
AVR CPU
INTERNAL
SCAN
CHAIN
FLASH
MEMORY
Address
Data
PC
Instruction
INSTRUCTION
REGISTER
ID
REGISTER
BREAKPOINT
UNIT
M
U
X
FLOW CONTROL
UNIT
BYPASS
REGISTER
DIGITAL
PERIPHERAL
UNITS
ANALOG
PERIPHERIAL
UNITS
Analog inputs
BREAKPOINT
SCAN CHAIN
JTAG / AVR CORE
COMMUNICATION
INTERFACE
ADDRESS
DECODER
OCD STATUS
AND CONTROL
Control & Clock lines
I/O PORT n
27.3 TAP - Test Access Port
The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins
constitute the Test Access Port – TAP. These pins are:
•
TMS: Test mode select. This pin is used for navigating through the TAP-controller state
machine.
•
•
TCK: Test Clock. JTAG operation is synchronous to TCK.
TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data
Register (Scan Chains).
•
TDO: Test Data Out. Serial output data from Instruction Register or Data Register.
The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not
provided.
When the JTAGEN Fuse is unprogrammed, these four TAP pins are normal port pins, and the
TAP controller is in reset. When programmed, the input TAP signals are internally pulled high
and the JTAG is enabled for Boundary-scan and programming. The device is shipped with this
fuse programmed.
For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is moni-
tored by the debugger to be able to detect external reset sources. The debugger can also pull
the RESET pin low to reset the whole system, assuming only open collectors on the reset line
are used in the application.
298
ATmega640/1280/1281/2560/2561
2549L–AVR–08/07
ATMEL [ ATMEL ]
