ATF16V8B
Input Test Waveforms and
Measurement Levels:
Output Test Loads:
Commercial
t
R
, t
F
< 5 ns (10% to 90%)
Pin Capacitance
(f = 1 MHz, T = 25°C)
(1)
Typ
C
IN
C
OUT
Note:
Max
8
8
Units
pF
pF
Conditions
V
IN
= 0V
V
OUT
= 0V
5
6
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power Up Reset
The registers in the ATF16V8Bs are designed to reset dur-
ing power up. At a point delayed slightly from V
CC
cross-
ing V
RST
, all registers will be reset to the low state. As a
result, the registered output state will always be high on
power-up.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the un-
certainty of how V
CC
actually rises in the system, the fol-
lowing conditions are required:
1) The V
CC
rise must be monotonic,
2) After reset occurs, all input and feedback setup times
must be met before driving the clock pin high, and
3) The clock must remain stable during t
PR
.
Parameter Description
t
PR
V
RST
Power-Up
Reset Time
Power-Up
Reset
Voltage
Typ
600
Max
1,000
Units
ns
3.8
4.5
V
Preload of Registered Outputs
The ATF16V8B’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC
file preload sequence will be done automatically by most
of the approved programmers after the programming.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF16V8B fuse patterns. Once programmed, fuse
verify and preload are inhibited. However, the 64-bit User
Signature remains accessible.
The security fuse should be programmed last, as its effect
is immediate.
1-11
ATMEL [ ATMEL CORPORATION ]
