Table 2-4.
AC Characteristics
Applicable over recommended operating range from T
A
=
−40°C
to + 85°C, V
CC
= +2.7V to + 5.5V,
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol
f
SK
Parameter
SK Clock Frequency
Test Condition
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
5.5V
Relative to SK
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
5.5V
Min
0
0
0
250
250
1000
250
250
1000
250
250
1000
50
50
200
100
100
400
0
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
5.5V
0.1
1M
3
100
100
400
250
250
1000
250
250
1000
250
250
1000
100
150
400
5
Typ
Max
2
1
0.25
Units
MHz
t
SKH
SK High Time
ns
t
SKL
SK Low Time
ns
t
CS
Minimum CS Low Time
ns
t
CSS
CS Setup Time
ns
t
DIS
t
CSH
t
DIH
DI Setup Time
CS Hold Time
DI Hold Time
Relative to SK
Relative to SK
Relative to SK
ns
ns
ns
t
PD1
Output Delay to “1”
AC Test
ns
t
PD0
Output Delay to “0”
AC Test
ns
t
SV
CS to Status Valid
AC Test
ns
t
DF
t
WP
Endurance
(1)
CS to DO in High
Impedance
Write Cycle Time
5.0V, 25°C
AC Test
CS = V
IL
ns
ms
Write Cycle
Note:
1. This parameter is ensured by characterization.
3. Functional Description
The AT93C46E is accessed via a simple and versatile three-wire serial communication inter-
face. Device operation is controlled by seven instructions issued by the host processor.
A valid
instruction starts with a rising edge of CS
and consists of a start bit (logic “1”) followed by the
appropriate op code and the desired memory address location.
4
AT93C46E
5207D–SEEPR–1/08
ATMEL [ ATMEL CORPORATION ]
