ERASE ALL (ERAL):
The Erase All (ERAL) instruction programs every bit in the mem-
ory array to the logic “1” state and is primarily used for testing purposes. The DO pin
outputs the Ready/Busy status of the part if CS is brought high after being kept low for a
minimum of 250 ns (t
CS
). The ERAL instruction is valid only at V
CC
= 5.0V
±
10%.
WRITE ALL (WRAL):
The Write All (WRAL) instruction programs all memory locations
with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy
status of the part if CS is brought high after being kept low for a minimum of 250 ns (t
CS
).
The WRAL instruction is valid only at V
CC
= 5.0V ± 10%.
ERASE/WRITE DISABLE (EWDS):
To protect against accidental data disturb, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be
executed after all programming operations. The operation of the Read instruction is
independent of both the EWEN and EWDS instructions and can be executed at any
time.
Timing Diagrams
Figure 2.
Synchronous Data Timing
µs
Note:
1. This is the minimum SK period.
Table 6.
Organization Key for Timing Diagrams
AT93C46 (1K)
I/O
A
N
D
N
x8
A
6
D
7
x 16
A
5
D
15
6
AT93C46
5140B–SEEPR–2/07
ATMEL [ ATMEL CORPORATION ]
