status of the part if CS is brought high after being kept low for a minimum of 250 ns (t
CS
).
The WRAL instruction is valid only at V
CC
= 5.0V
±
10%.
ERASE/WRITE DISABLE (EWDS):
To protect against accidental data disturb, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be
executed after all programming operations. The operation of the Read instruction is
independent of both the EWEN and EWDS instructions and can be executed at any
time.
Timing Diagrams
Figure 2.
Synchronous Data Timing
µ
s
(1)
Note:
1. This is the minimum SK period.
Table 6.
Organization Key for Timing Diagrams
AT93C46E
I/O
A
N
D
N
x 16
A
5
D
15
6
AT93C46E [Preliminary]
5207A–SEEPR–1/07
ATMEL [ ATMEL CORPORATION ]
