AT91RM9200
– Four Pairs of Address Comparators
– Two Data Comparators
– Eight Memory Map Decoder Inputs
– Two Counters
– One Sequencer
– One 18-byte FIFO
• IEEE1149.1 JTAG Boundary Scan on all Digital Pins
3.3
Boot Program
• Default Boot Program stored in ROM-based products
• Downloads and runs an application from external storage media into internal SRAM
• Downloaded code size depends on embedded SRAM size
• Automatic detection of valid application
• Bootloader supporting a wide range of non-volatile memories
– SPI DataFlash
®
connected on SPI NPCS0
– Two-wire EEPROM
– 8-bit parallel memories on NCS0
• Boot Uploader in case no valid program is detected in external NVM and supporting several
communication media
• Serial communication on a DBGU (XModem protocol)
• USB Device Port (DFU Protocol)
3.4
Embedded Software Services
• Compliant with ATPCS
• Compliant with AINSI/ISO Standard C
• Compiled in ARM/Thumb Interworking
• ROM Entry Service
• Tempo, Xmodem and DataFlash services
• CRC and Sine tables
3.5
Reset Controller
• Two reset input lines (NRST and NTRST) providing, respectively:
• Initialization of the User Interface registers (defined in the user interface of each peripheral)
and:
– Sample the signals needed at bootup
– Compel the processor to fetch the next instruction at address zero.
• Initialization of the embedded ICE TAP controller.
3.6
Memory Controller
• Programmable Bus Arbiter handling four Masters
– Internal Bus is shared by ARM920T, PDC, USB Host Port and Ethernet MAC
Masters
5
1768E–ATARM–30-Sep-05
ATMEL [ ATMEL CORPORATION ]
