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AT90PWM3B-16SU 参数 Datasheet PDF下载

AT90PWM3B-16SU图片预览
型号: AT90PWM3B-16SU
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器具有8K字节的系统内可编程闪存 [8-bit Microcontroller with 8K Bytes In-System Programmable Flash]
分类和应用: 闪存微控制器
文件页数/大小: 361 页 / 6022 K
品牌: ATMEL [ ATMEL ]
 浏览型号AT90PWM3B-16SU的Datasheet PDF文件第94页浏览型号AT90PWM3B-16SU的Datasheet PDF文件第95页浏览型号AT90PWM3B-16SU的Datasheet PDF文件第96页浏览型号AT90PWM3B-16SU的Datasheet PDF文件第97页浏览型号AT90PWM3B-16SU的Datasheet PDF文件第99页浏览型号AT90PWM3B-16SU的Datasheet PDF文件第100页浏览型号AT90PWM3B-16SU的Datasheet PDF文件第101页浏览型号AT90PWM3B-16SU的Datasheet PDF文件第102页  
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting  
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-  
form generation to be used, see Table 14-8. Modes of operation supported by the Timer/Counter  
unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of  
Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 90).  
Table 14-8. Waveform Generation Mode Bit Description  
Timer/Count  
er Mode of  
Update of  
OCRx at  
TOV Flag  
Mode WGM02 WGM01 WGM00 Operation  
TOP  
Set on(1)(2)  
0
1
0
0
0
0
0
1
Normal  
0xFF  
Immediate  
TOP  
MAX  
PWM, Phase  
Correct  
0xFF  
BOTTOM  
2
3
4
0
0
1
1
1
0
0
1
0
CTC  
OCRA Immediate  
MAX  
MAX  
Fast PWM  
Reserved  
0xFF  
TOP  
PWM, Phase  
Correct  
5
1
0
1
OCRA  
TOP  
BOTTOM  
6
7
1
1
1
1
0
1
Reserved  
Fast PWM  
OCRA  
TOP  
TOP  
Notes: 1. MAX  
= 0xFF  
2. BOTTOM = 0x00  
14.8.2  
Timer/Counter Control Register B – TCCR0B  
Bit  
7
FOC0A  
W
6
FOC0B  
W
5
4
3
2
CS02  
R
1
0
CS00  
R/W  
0
WGM02  
CS01  
R/W  
0
TCCR0B  
Read/Write  
Initial Value  
R
0
R
0
R
0
0
0
0
• Bit 7 – FOC0A: Force Output Compare A  
The FOC0A bit is only active when the WGM bits specify a non-PWM mode.  
However, for ensuring compatibility with future devices, this bit must be set to zero when  
TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit,  
an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is  
changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a  
strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the  
forced compare.  
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using  
OCR0A as TOP.  
The FOC0A bit is always read as zero.  
• Bit 6 – FOC0B: Force Output Compare B  
The FOC0B bit is only active when the WGM bits specify a non-PWM mode.  
However, for ensuring compatibility with future devices, this bit must be set to zero when  
TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit,  
an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is  
changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is implemented as a  
98  
AT90PWM2/3/2B/3B  
4317J–AVR–08/10  
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