15.2
15.3
15.4
15.5
15.6
15.7
15.8
15.9
Accessing 16-bit Registers 104
Timer/Counter Clock Sources 107
Counter Unit 108
Input Capture Unit 109
Output Compare Units 110
Compare Match Output Unit 112
Modes of Operation 113
Timer/Counter Timing Diagrams 121
15.10 16-bit Timer/Counter Register Description 122
16 Power Stage Controller – (PSC0, PSC1 & PSC2) 129
16.1
16.2
16.3
16.4
16.5
16.6
16.7
16.8
16.9
Features 129
Overview 129
PSC Description 130
Signal Description 132
Functional Description 134
Update of Values 139
Enhanced Resolution 139
PSC Inputs 143
PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait 148
16.10 PSC Input Mode 2: Stop signal, Execute Opposite Dead-Time and Wait 149
16.11 PSC Input Mode 3: Stop signal, Execute Opposite while Fault active 150
16.12 PSC Input Mode 4: Deactivate outputs without changing timing. 150
16.13 PSC Input Mode 5: Stop signal and Insert Dead-Time 151
16.14 PSC Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait. 152
16.15 PSC Input Mode 7: Halt PSC and Wait for Software Action 152
16.16 PSC Input Mode 8: Edge Retrigger PSC 152
16.17 PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC 153
16.18 PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Disactivate Out-
put 154
16.19 PSC2 Outputs 157
16.20 Analog Synchronization 157
16.21 Interrupt Handling 158
16.22 PSC Synchronization 158
16.23 PSC Clock Sources 159
16.24 Interrupts 160
16.25 PSC Register Definition 161
iii
AT90PWM2/3/2B/3B
4317J–AVR–08/10
ATMEL [ ATMEL ]
