All the receiver error flags are valid only when the RxC bit is set and until the UDR register is
read.
19.5.5.1
19.5.5.2
Parity Checker
The parity checker of the EUSART is available only when data bits are level encoded and
behaves as is USART mode (See Parity checker of the USART).
OverRun
The Data OverRun (DOR bit of USCRA) flag indicates data loss due to a receiver buffer full con-
dition. This flag operates as in USART mode (See USART section).
19.6 EUSART Registers Description
19.6.1
USART I/O Data Register – UDR
Bit
7
6
5
4
3
2
1
0
RXB[7:0]
TXB[7:0]
UDR (Read)
UDR (Write)
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
• Bit 7:0 – RxB7:0: Receive Data Buffer (read access)
• Bit 7:0 – TxB7:0: Transmit Data Buffer (write access)
This register is common to the USART and EUSART interfaces for Transmit Data Buffer Regis-
ter and Receive Data Buffer Register. See description for UDR register in USART.
19.6.2
EUSART I/O Data Register – EUDR
Bit
7
6
5
4
3
2
1
0
RXB[15:8]
TXB[15:8]
EUDR (Read)
EUDR (Write)
Read/Write
Initial Value
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
0
• Bit 7:0 – RxB15:8: Receive Data Buffer (read access)
• Bit 7:0 – TxB15:8: Transmit Data Buffer (write access)
This register provide an extension to the UDR register when EUSART is used with more than 8
bits.
19.6.2.1
19.6.2.2
UDR/EUDR data access with character size up to 8 bits
When the EUSART is used with 8 or less bits, only the UDR register is used for dta access.
UDR/EUDR data access with 9 bits per character
When the EUSART is used with 9 bits character, the behavior is different of the standart USART
mode, the UDR register is used in combinaison with the first bit of EUDR (EUDR:0) for data
access, the RxB8/TxB8 bit is not used.
220
AT90PWM2/3/2B/3B
4317J–AVR–08/10
ATMEL [ ATMEL ]
