5.1
Auxiliary Register
AUXR – Auxiliary Register
Reset Value = XXXX XXX0B
The AUXR Register contains a single active bit called DISALE.
Table 5-2.
AUXR Address = 8EH
Not Bit Addressable
–
Bit
Symbol
DISALE
7
–
6
Function
–
5
–
4
–
3
–
2
Intel_Pwd_Exit
1
DISALE
0
When DISALE = 0, ALE is emitted at a constant rate of 1/6 the oscillator frequency (except during MOVX when 1
ALE pulse is missing). When DISALE = 1, ALE is active only during a MOVX or MOVC instruction.
When set, this bit configures the interrupt driven exit from power-down to resume execution on the rising edge of
the interrupt signal. When this bit is cleared, the execution resumes after a self-timed interval (nominal 2 ms)
referenced from the falling edge of the interrupt signal.
Intel_Pwd_Exit
5.2
Clock Register
CLKREG – Clock Register
Reset Value = XXXX XXX0B
The CLKREG register contains a single active bit called X2.
Table 5-3.
CLKREG Address = 8FH
Not Bit Addressable
–
Bit
Symbol
7
Function
–
6
–
5
–
4
–
3
–
2
–
1
X2
0
X2
When X2 = 0, the oscillator frequency (at XTAL1 pin) is internally divided by 2 before it is used as the device system
frequency.
When X2 = 1, the divider by 2 is no longer used and the XTAL1 frequency becomes the device system frequency. This
enables the user to choose a 6 MHz crystal instead of a 12 MHz crystal, for example, in order to reduce EMI.
5.3
SPI Registers
Control and status bits for the Serial Peripheral Interface are contained in registers SPCR (see
and SPSR (see
The SPI data bits are contained
in the SPDR register. In normal SPI mode, writing the SPI data register during serial data trans-
fer sets the Write Collision bit (WCOL) in the SPSR register. In enhanced SPI mode, the SPDR
is also write double-buffered because WCOL works as a Write Buffer Full Flag instead of being a
collision flag. The values in SPDR are not changed by Reset.
5.4
Interrupt Registers
The global interrupt enable bit and the individual interrupt enable bits are in the IE register. In
addition, the individual interrupt enable bit for the SPI is in the SPCR register. Four priorities can
be set for each of the six interrupt sources in the IP and IPH registers.
IPH bits have the same functions as IP bits, except IPH has higher priority than IP. By using IPH
in conjunction with IP, a priority level of 0, 1, 2, or 3 may be set for each interrupt.
8
AT89S8253
3286H–MICRO–9/05
ATMEL [ ATMEL CORPORATION ]
