AT89S8252
Serial Port Timing: Shift Register Mode Test Conditions
The values in this table are valid for VCC = 4.0V to 6V and Load Capacitance = 80 pF.
Variable Oscillator
Symbol
tXLXL
Parameter
Min
Max
Units
µs
Serial Port Clock Cycle Time
12tCLCL
10tCLCL - 133
2tCLCL - 117
0
tQVXH
tXHQX
tXHDX
tXHDV
Output Data Setup to Clock Rising Edge
Output Data Hold after Clock Rising Edge
Input Data Hold after Clock Rising Edge
Clock Rising Edge to Input Data Valid
ns
ns
ns
10tCLCL - 133
ns
Shift Register Mode Timing Waveforms
AC Testing Input/Output Waveforms(1)
Note:
1. AC Inputs during testing are driven at VCC - 0.5V
for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0.
Float Waveforms(1)
Note:
1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to
float when a 100 mV change from the loaded VOH/VOL level occurs.
35
0401G–MICRO–3/06
ATMEL [ ATMEL ]
