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AT89S53-24JC 参数 Datasheet PDF下载

AT89S53-24JC图片预览
型号: AT89S53-24JC
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器,带有12K字节的闪存 [8-Bit Microcontroller with 12K Bytes Flash]
分类和应用: 闪存微控制器
文件页数/大小: 32 页 / 474 K
品牌: ATMEL [ ATMEL ]
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Figure 9. SPI Transfer Format with CPHA = 1  
SCK CYCLE #  
1
2
3
4
5
6
7
8
(FOR REFERENCE)  
SCK (CPOL=0)  
SCK (CPOL=1)  
MOSI  
(FROM MASTER)  
MSB  
MSB  
6
5
5
4
3
3
2
1
1
LSB  
MISO  
(FROM SLAVE)  
6
4
2
LSB  
*
SS (TO SLAVE)  
*Not defined but normally LSB of previously transmitted character  
mented. User software should not write 1s to these bit posi-  
tions, since they may be used in future AT89 products.  
Interrupts  
The AT89S53 has a total of six interrupt vectors: two exter-  
nal interrupts (INT0 and INT1), three timer interrupts (Tim-  
ers 0, 1, and 2), and the serial port interrupt. These inter-  
rupts are all shown in Figure 10.  
Timer 2 interrupt is generated by the logical OR of bits TF2  
and EXF2 in register T2CON. Neither of these flags is  
cleared by hardware when the service routine is vectored  
to. In fact, the service routine may have to determine  
whether it was TF2 or EXF2 that generated the interrupt,  
and that bit will have to be cleared in software.  
Each of these interrupt sources can be individually enabled  
or disabled by setting or clearing a bit in Special Function  
Register IE. IE also contains a global disable bit, EA, which  
disables all interrupts at once.  
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at  
S5P2 of the cycle in which the timers overflow. The values  
are then polled by the circuitry in the next cycle. However,  
the Timer 2 flag, TF2, is set at S2P2 and is polled in the  
same cycle in which the timer overflows.  
Note that Table 10 shows that bit position IE.6 is unimple-  
mented. In the AT89C51, bit position IE.5 is also unimple-  
Table 10. Interrupt Enable (IE) Register  
Figure 10. Interrupt Sources  
(MSB)  
EA  
(LSB)  
EX0  
ET2  
ES  
ET1  
EX1  
ET0  
Enable Bit = 1 enables the interrupt.  
Enable Bit = 0 disables the interrupt.  
Symbol  
Position  
Function  
EA  
IE.7  
Disables all interrupts. If EA = 0, no interrupt  
is acknowledged. If EA = 1, each interrupt  
source is individually enabled or disabled by  
setting or clearing its enable bit.  
IE.6  
IE.5  
IE.4  
IE.3  
IE.2  
IE.1  
IE.0  
Reserved.  
ET2  
ES  
Timer 2 interrupt enable bit.  
SPI and UART interrupt enable bit.  
Timer 1 interrupt enable bit.  
External interrupt 1 enable bit.  
Timer 0 interrupt enable bit.  
External interrupt 0 enable bit.  
ET1  
EX1  
ET0  
EX0  
User software should never write 1s to unimplemented bits, because  
they may be used in future AT89 products.  
AT89S53  
4-232  
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