欢迎访问ic37.com |
会员登录 免费注册
发布采购

AT89S53-24JC 参数 Datasheet PDF下载

AT89S53-24JC图片预览
型号: AT89S53-24JC
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器,带有12K字节的闪存 [8-Bit Microcontroller with 12K Bytes Flash]
分类和应用: 闪存微控制器
文件页数/大小: 32 页 / 474 K
品牌: ATMEL [ ATMEL ]
 浏览型号AT89S53-24JC的Datasheet PDF文件第11页浏览型号AT89S53-24JC的Datasheet PDF文件第12页浏览型号AT89S53-24JC的Datasheet PDF文件第13页浏览型号AT89S53-24JC的Datasheet PDF文件第14页浏览型号AT89S53-24JC的Datasheet PDF文件第16页浏览型号AT89S53-24JC的Datasheet PDF文件第17页浏览型号AT89S53-24JC的Datasheet PDF文件第18页浏览型号AT89S53-24JC的Datasheet PDF文件第19页  
AT89S53  
clock output in the master mode but is the clock input in the  
slave mode. Writing to the SPI data register of the master  
CPU starts the SPI clock generator, and the data written  
shifts out of the MOSI pin and into the MOSI pin of the  
slave CPU. After shifting one byte, the SPI clock generator  
stops, setting the end of transmission flag (SPIF). If both  
the SPI interrupt enable bit (SPIE) and the serial port inter-  
rupt enable bit (ES) are set, an interrupt is requested.  
the SPI port is deactivated and the MOSI/P1.5 pin can be  
used as an input.  
There are four combinations of SCK phase and polarity  
with respect to serial data, which are determined by control  
bits CPHA and CPOL. The SPI data transfer formats are  
shown in Figures 8 and 9.  
The Slave Select input, SS/P1.4, is set low to select an  
individual SPI device as a slave. When SS/P1.4 is set high,  
Figure 7. SPI Master-Slave Interconnection  
MSB  
MASTER  
LSB  
MSB  
SLAVE  
LSB  
MISO MISO  
MOSI MOSI  
8-BIT SHIFT REGISTER  
8-BIT SHIFT REGISTER  
SCK  
SS  
SCK  
SS  
SPI  
CLOCK GENERATOR  
VCC  
Figure 8. SPI transfer Format with CPHA = 0  
*Not defined but normally MSB of character just received  
4-231  
 复制成功!