AT89S53
Serial Port Timing: Shift Register Mode Test Conditions
The values in this table are valid for VCC = 4.0V to 6V and Load Capacitance = 80 pF.
Symbol
Parameter
12 MHz Oscillator
Min Max
Variable Oscillator
Units
Min
Max
tXLXL
Serial Port Clock Cycle Time
1.0
12tCLCL
µs
tQVXH
Output Data Setup to Clock Rising
Edge
700
10tCLCL - 133
ns
tXHQX
tXHDX
tXHDV
Output Data Hold After Clock Rising
Edge
50
0
2tCLCL - 117
0
ns
ns
ns
Input Data Hold After Clock Rising
Edge
Clock Rising Edge to Input Data
Valid
700
10tCLCL - 133
Shift Register Mode Timing Waveforms
(1)
(1)
AC Testing Input/Output Waveforms
Float Waveforms
Notes: 1. AC Inputs during testing are driven at VCC - 0.5V
for a logic 1 and 0.45V for a logic 0. Timing mea-
surements are made at VIH min. for a logic 1 and VIL
max. for a logic 0.
Notes: 1. For timing purposes, a port pin is no longer floating
when a 100 mV change from load voltage occurs. A
port pin begins to float when a 100 mV change from
the loaded VOH/VOL level occurs.
4-245
ATMEL [ ATMEL ]
