Figure 9. SPI Transfer Format with CPHA = 1
SCK CYCLE #
1
2
3
4
5
6
7
8
(FOR REFERENCE)
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
(FROM MASTER)
MSB
MSB
6
5
5
4
3
3
2
1
1
LSB
MISO
(FROM SLAVE)
6
4
2
LSB
*
SS (TO SLAVE)
*Not defined but normally LSB of previously transmitted character
Interrupts
The AT89S53 has a total of six interrupt vectors: two exter-
nal interrupts (INT0 and INT1), three timer interrupts
(Timers 0, 1, and 2), and the serial port interrupt. These
interrupts are all shown in Figure 10.
ET0
EX0
IE.1
IE.0
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
User software should never write 1s to unimplemented bits, because
they may be used in future AT89 products.
Each of these interrupt sources can be individually enabled
or disabled by setting or clearing a bit in Special Function
Register IE. IE also contains a global disable bit, EA, which
disables all interrupts at once.
Figure 10. Interrupt Sources
Note that Table 10 shows that bit position IE.6 is unimple-
mented. In the AT89C51, bit position IE.5 is also
unimplemented. User software should not write 1s to these
bit positions, since they may be used in future AT89
products.
Table 10. Interrupt Enable (IE) Register
(MSB)(LSB)
EA
–
ET2
ES
ET1
EX1
ET0
EX0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables the interrupt.
Symbol
Position
Function
EA
IE.7
Disables all interrupts. If EA = 0, no interrupt
is acknowledged. If EA = 1, each interrupt
source is individually enabled or disabled by
setting or clearing its enable bit.
–
IE.6
IE.5
IE.4
IE.3
IE.2
Reserved.
ET2
ES
Timer 2 interrupt enable bit.
SPI and UART interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
ET1
EX1
AT89S53
16
ATMEL [ ATMEL ]
