Figure 9.
SPI Transfer Format with CPHA = 1
SCK CYCLE #
(FOR REFERENCE)
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
(FROM MASTER)
MISO
(FROM SLAVE)
SS (TO SLAVE)
MSB
6
6
5
5
4
4
3
3
2
2
1
1
LSB
LSB
1
2
3
4
5
6
7
8
*
MSB
*Not defined but normally LSB of previously transmitted character
Interrupts
The AT89S53 has a total of six interrupt vectors: two exter-
nal interrupts (INT0 and INT1), three timer interrupts
(Timers 0, 1, and 2), and the serial port interrupt. These
interrupts are all shown in Figure 10.
Each of these interrupt sources can be individually enabled
or disabled by setting or clearing a bit in Special Function
Register IE. IE also contains a global disable bit, EA, which
disables all interrupts at once.
Note that Table 10 shows that bit position IE.6 is unimple-
mented. In the A T89 C5 1, bit positi on IE.5 is als o
unimplemented. User software should not write 1s to these
bit positions, since they may be used in future AT89
products.
Table 10.
Interrupt Enable (IE) Register
(MSB)(LSB)
EA
ET0
EX0
IE.1
IE.0
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
User software should never write 1s to unimplemented bits, because
they may be used in future AT89 products.
Figure 10.
Interrupt Sources
–
ET2
ES
ET1
EX1
ET0
EX0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables the interrupt.
Symbol
EA
Position
IE.7
Function
Disables all interrupts. If EA = 0, no interrupt
is acknowledged. If EA = 1, each interrupt
source is individually enabled or disabled by
setting or clearing its enable bit.
Reserved.
Timer 2 interrupt enable bit.
SPI and UART interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
–
ET2
ES
ET1
EX1
IE.6
IE.5
IE.4
IE.3
IE.2
16
AT89S53
ATMEL [ ATMEL CORPORATION ]
