AT89C51
Serial Port Timing: Shift Register Mode Test Conditions
(VCC = 5.0 V ± 20%; Load Capacitance = 80 pF)
Symbol
Parameter
12 MHz Osc
Variable Oscillator
Units
Min
1.0
700
50
Max
Min
Max
tXLXL
tQVXH
tXHQX
tXHDX
tXHDV
Serial Port Clock Cycle Time
12tCLCL
10tCLCL-133
2tCLCL-117
0
µs
ns
ns
ns
ns
Output Data Setup to Clock Rising Edge
Output Data Hold After Clock Rising Edge
Input Data Hold After Clock Rising Edge
Clock Rising Edge to Input Data Valid
0
700
10tCLCL-133
Shift Register Mode Timing Waveforms
INSTRUCTION
ALE
0
1
2
3
4
5
6
7
8
tXLXL
CLOCK
tQVXH
tXHQX
WRITE TO SBUF
0
1
2
tXHDX
3
4
5
6
7
SET TI
tXHDV
OUTPUT DATA
CLEAR RI
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
INPUT DATA
(1)
(1)
AC Testing Input/Output Waveforms
Float Waveforms
VCC - 0.5V
+ 0.1V
- 0.1V
VOL
VLOAD
0.2 VCC + 0.9V
Timing Reference
Points
VLOAD
TEST POINTS
- 0.1V
0.2 VCC - 0.1V
0.45V
VLOAD
+ 0.1V
VOL
Note:
1. AC Inputs during testing are driven at VCC - 0.5V for Note:
a logic 1 and 0.45V for a logic 0. Timing measure-
ments are made at VIH min. for a logic 1 and VIL
max. for a logic 0.
1. For timing purposes, a port pin is no longer floating
when a 100 mV change from load voltage occurs. A
port pin begins to float when 100 mV change from
the loaded V /V level occurs.
OH OL
4-41
ATMEL [ ATMEL ]
