欢迎访问ic37.com |
会员登录 免费注册
发布采购

AT89C2051X2-8PC 参数 Datasheet PDF下载

AT89C2051X2-8PC图片预览
型号: AT89C2051X2-8PC
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器与2K字节的闪存 [8-bit Microcontroller with 2K Bytes Flash]
分类和应用: 闪存微控制器
文件页数/大小: 19 页 / 205 K
品牌: ATMEL [ ATMEL CORPORATION ]
 浏览型号AT89C2051X2-8PC的Datasheet PDF文件第1页浏览型号AT89C2051X2-8PC的Datasheet PDF文件第2页浏览型号AT89C2051X2-8PC的Datasheet PDF文件第3页浏览型号AT89C2051X2-8PC的Datasheet PDF文件第5页浏览型号AT89C2051X2-8PC的Datasheet PDF文件第6页浏览型号AT89C2051X2-8PC的Datasheet PDF文件第7页浏览型号AT89C2051X2-8PC的Datasheet PDF文件第8页浏览型号AT89C2051X2-8PC的Datasheet PDF文件第9页  
Oscillator
Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which
can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz
crystal or ceramic resonator may be used. To drive the device from an external clock
source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.
There are no requirements on the duty cycle of the external clock signal, since the input
to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and
maximum voltage high and low time specifications must be observed.
Figure 1.
Oscillator Connections
Note:
C1, C2 = 30 pF
±
10 pF for Crystals
= 40 pF
±
10 pF for Ceramic Resonators
Figure 2.
External Clock Drive Configuration
X2 Mode Description
The clock for the entire circuit and peripherals is normally divided by 2 before being
used by the CPU core and peripherals. This allows any cyclic ratio (duty cycle) to be
accepted on XTAL1 input. In X2 mode, as this divider is bypassed, the signals on
XTAL1 must have a cyclic ratio (duty cycle) between 40% to 60%. Figure 3 shows the
clock generation block diagram.
Figure 3.
Clock Generation Block Diagram
X2 Mode
(XTAL1)/2
State Machine: 6 Clock Cycles
CPU Control
XTAL1
F
XTAL
÷
2
F
OSC
4
AT89C2051x2
3285B–MICRO–10/03