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Serial Port Timing: Shift Register Mode Test Conditions
VCC = 5.0V 20%; Load Capacitance = 80 pF
12 MHz Osc
Variable Oscillator
Symbol
tXLXL
Parameter
Min
1.0
700
50
Max
Min
12tCLCL
10tCLCL-133
2tCLCL-117
0
Max
Units
µs
Serial Port Clock Cycle Time
tQVXH
tXHQX
tXHDX
tXHDV
Output Data Setup to Clock Rising Edge
Output Data Hold after Clock Rising Edge
Input Data Hold after Clock Rising Edge
Clock Rising Edge to Input Data Valid
ns
ns
0
ns
700
10tCLCL-133
ns
Shift Register Mode Timing Waveforms
AC Testing Input/Output Waveforms(1)
Note:
1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH
min. for a logic 1 and VIL max. for a logic 0.
Float Waveforms(1)
Note:
1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to
float when 100 mV change from the loaded VOH/VOL level occurs.
14
AT89C2051x2
3285B–MICRO–10/03
ATMEL [ ATMEL ]
