AT45DB642D
3. Block Diagram
WP
FLASH MEMORY ARRAY
PAGE (1024/1056 BYTES)
BUFFER 1 (1024/1056 BYTES)
BUFFER 2 (1024/1056 BYTES)
SCK/CLK
CS
RESET
VCC
GND
RDY/BUSY
SER/BYTE
I/O INTERFACE
SI SO
I/O7 - I/O0
4. Memory Array
To provide optimal flexibility, the memory array of the AT45DB642D is divided into three levels of
granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illus-
trates the breakdown of each level and details the number of pages per sector and block. All
program operations to the DataFlash occur on a page by page basis. The erase operations can
be performed at the chip, sector, block or page level.
Figure 4-1.
Memory Architecture Diagram
BLOCK ARCHITECTURE
SECTOR 0
SECTOR 1
BLOCK 0
SECTOR ARCHITECTURE
SECTOR 0a = 8 Pages
8192/8,448 bytes
SECTOR 0b = 248 Pages
253,952/261,888 bytes
PAGE ARCHITECTURE
8 Pages
PAGE 0
PAGE 1
BLOCK 0
BLOCK 1
BLOCK 2
SECTOR 2 = 256 Pages
262,144/270,336
bytes
SECTOR 2
BLOCK 1
SECTOR 1 = 256 Pages
262,144/270,336 bytes
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
PAGE 6
PAGE 7
PAGE 8
PAGE 9
SECTOR 30 = 256 Pages
262,144/270,336 bytes
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
SECTOR 31 = 256 Pages
262,144/270,336 bytes
BLOCK 1022
BLOCK 1023
Block = 8,192/8,448 bytes
PAGE 8,190
PAGE 8,190
Page = 1,024/1,056 bytes
5
3542K–DFLASH–04/09
ATMEL [ ATMEL CORPORATION ]
