3. Block Diagram
WP
FLASH MEMORY ARRAY
PAGE (256/264 BYTES)
BUFFER 1 (256/264 BYTES)
BUFFER 2 (256/264 BYTES)
SCK
CS
RESET
VCC
GND
SI
I/O INTERFACE
SO
4. Memory Array
To provide optimal flexibility, the memory array of the AT45DB081D is divided into three levels of granularity comprising of
sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and details the
number of pages per sector and block. All program operations to the DataFlash occur on a page by page basis. The erase
operations can be performed at the chip, sector, block or page level.
Figure 4-1.
Memory Architecture Diagram
BLOCK ARCHITECTURE
SECTOR
0a
SECTOR
0b
BLOCK 0
BLOCK 1
BLOCK 2
SECTOR
ARCHITECTURE
SECTOR
0a =
8
Pages
2,048/2,112 bytes
PAGE ARCHITECTURE
8
Pages
BLOCK 0
PAGE 0
PAGE 1
SECTOR
0b = 248 Pages
63,488/65,472 bytes
PAGE 6
PAGE 7
PAGE
8
BLOCK
30
BLOCK
31
SECTOR
1 = 256 Pages
65,536/67,584 bytes
BLOCK
33
SECTOR
2 = 256 Pages
65,536/67,584
bytes
SECTOR
1
BLOCK 1
BLOCK
32
PAGE 9
PAGE 14
PAGE 15
BLOCK 62
BLOCK 63
BLOCK 64
SECTOR
14 = 256 Pages
65,536/67,584 bytes
BLOCK 65
PAGE 16
PAGE 17
PAGE 18
SECTOR
15 = 256 Pages
65,536/67,584 bytes
BLOCK 510
BLOCK 511
PAGE 4,094
PAGE 4,095
Block = 2,048/2,112 bytes
Page = 256/264 bytes
4
AT45DB081D
3596I–DFLASH–4/08
ATMEL [ ATMEL CORPORATION ]
