AT45DB041D
28. Revision History
Revision Level – Revision Date History
A – October 2005
B – March 2006
Initial Release
Added “Preliminary”.
Added text, in “Programming the Configuration Register”, to
indicate that power cycling is required to switch to “power of 2” page
size after the opcode enable has been executed.
Added “Legacy Commands” table.
Corrected typographical errors.
Corrected typographical errors.
Added errata regarding Chip Erase.
Removed “Preliminary”.
C – June 2006
D – July 2006
E – August 2006
F – November 2006
G – February 2007
Removed RDY/BUSY pin references.
Changed page size description from 512 to 256 in Table 15-6.
Changed page size description from 528 to 264 in Table 15-7.
Added additional text for “power of 2” binary page size option.
H – March 2007
Removed SER/BYTE statement from SI and SO pin descriptions in
Table 2-1.
Changed the number of don’t care bits from 17 to 16 for sector 1-15
erase in Section 7.6.
Corrected the density code description from 16-Mbit to 4-Mbit in
Section 14.1.2.
I – April 2007
Changed A16 address bit for opcode 7Ch from “x” to “A” in Table
15-6.
Chagned PA8 address bit for opcode 7Ch from “x” to “P” in Table
15-7.
Changed tXFR and tCOMP values from 400 µs to 200 µs.
Changed tVCSL from 50 µs to 70 µs.
J – August 2007
Changed tRDPD from 30 µs to 35 µs.
K – December 2007
Changed Note 1 on page 14 from “0 through 15” to “0 through 7”.
The Chip Erase command is supported on devices with date code
0810 and later.
Added Chip Erase time.
L – April 2008
Added part nuber ordering code details for suffixes SL954/955.
Added ordering code detail.
51
3595L–DFLASH–4/08
ATMEL [ ATMEL ]
