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AT45DB041D-SU-SL954 参数 Datasheet PDF下载

AT45DB041D-SU-SL954图片预览
型号: AT45DB041D-SU-SL954
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位2.5伏或2.7伏的DataFlash [4-megabit 2.5-volt or 2.7-volt DataFlash]
分类和应用: 闪存存储内存集成电路光电二极管异步传输模式ATM时钟
文件页数/大小: 53 页 / 1649 K
品牌: ATMEL [ ATMEL ]
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AT45DB041D  
10.2.2  
Reading the Security Register  
The Security Register can be read by first asserting the CS pin and then clocking in an opcode  
of 77H followed by three dummy bytes. After the last don't care bit has been clocked in, the con-  
tent of the Security Register can be clocked out on the SO pins. After the last byte of the  
Security Register has been read, additional pulses on the SCK pin will simply result in undefined  
data being output on the SO pins.  
Deasserting the CS pin will terminate the Read Security Register operation and put the SO pins  
into a high-impedance state.  
Figure 10-4. Read Security Register  
CS  
SI  
Opcode  
X
X
X
Data Byte  
n
Data Byte  
n + 1  
Data Byte  
n + x  
SO  
Each transition  
represents 8 bits  
11. Additional Commands  
11.1 Main Memory Page to Buffer Transfer  
A page of data can be transferred from the main memory to either buffer 1 or buffer 2. To start  
the operation for the DataFlash standard page size (264 bytes), a 1-byte opcode, 53H for buffer  
1 and 55H for buffer 2, must be clocked into the device, followed by three address bytes com-  
prised of 4 don’t care bits, 11 page address bits (PA10 - PA0), which specify the page in main  
memory that is to be transferred, and 9 don’t care bits. To perform a main memory page to buffer  
transfer for the binary page size (256 bytes), the opcode 53H for buffer 1 or 55H for buffer 2,  
must be clocked into the device followed by three address bytes consisting of 5 don’t care bits,  
11 page address bits (A18 - A8) which specify the page in the main memory that is to be trans-  
ferred, and 8 don’t care bits. The CS pin must be low while toggling the SCK pin to load the  
opcode and the address bytes from the input pin (SI). The transfer of the page of data from the  
main memory to the buffer will begin when the CS pin transitions from a low to a high state. Dur-  
ing the transfer of a page of data (tXFR), the status register can be read to determine whether the  
transfer has been completed.  
11.2 Main Memory Page to Buffer Compare  
A page of data in main memory can be compared to the data in buffer 1 or buffer 2. To initiate  
the operation for the DataFlash standard page size, a 1-byte opcode, 60H for buffer 1 and 61H  
for buffer 2, must be clocked into the device, followed by three address bytes consisting of  
4 don’t care bits, 11 page address bits (PA10 - PA0) that specify the page in the main memory  
that is to be compared to the buffer, and 9 don’t care bits. To start a main memory page to buffer  
compare for a binary page size, the opcode 60H for buffer 1 or 61H for buffer 2, must be clocked  
into the device followed by three address bytes consisting of 5 don’t care bits, 11 page address  
bits (A18 - A8) that specify the page in the main memory that is to be compared to the buffer,  
and 8 don’t care bits. The CS pin must be low while toggling the SCK pin to load the opcode and  
21  
3595L–DFLASH–4/08  
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