3. Block Diagram
WP
FLASH MEMORY ARRAY
PAGE (512/528 BYTES)
BUFFER 1 (512/528 BYTES)
BUFFER 2 (512/528 BYTES)
SCK
CS
I/O INTERFACE
RESET
VCC
GND
RDY/BUSY
SI
SO
4. Memory Array
To provide optimal flexibility, the memory array of the AT45DB321D is divided into three levels of granularity comprising of
sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and details the
number of pages per sector and block. All program operations to the DataFlash occur on a page by page basis. The erase
operations can be performed at the chip, sector, block or page level.
Figure 4-1. Memory Architecture Diagram
SECTOR ARCHITECTURE
BLOCK ARCHITECTURE
PAGE ARCHITECTURE
BLOCK 0
BLOCK 1
BLOCK 2
8 Pages
PAGE 0
PAGE 1
SECTOR 0a
SECTOR 0a = 8 Pages
4,096/4,224 bytes
SECTOR 0b = 120 Pages
61,440/63,360 bytes
PAGE 6
PAGE 7
PAGE 8
PAGE 9
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
SECTOR 1 = 128 Pages
65,536/67,584 bytes
SECTOR 2 = 128 Pages
65,536/67,584 bytes
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
BLOCK 126
BLOCK 127
BLOCK 128
BLOCK 129
SECTOR 62 = 128 Pages
65,536/67,584 bytes
SECTOR 63 = 128 Pages
65,536/67,586 bytes
BLOCK 1,022
PAGE 8,190
PAGE 8,191
BLOCK 1,023
Block = 4,096/4,224 bytes
Page = 512/528 bytes
4
AT45DB321D [Preliminary]
3597H–DFLASH–02/07
ATMEL [ ATMEL ]
