21.6 Reset Timing
CS
t
t
CSS
REC
SCK
RESET
t
RST
HIGH IMPEDANCE
HIGH IMPEDANCE
SO (OUTPUT)
SI (INPUT)
Note:
The CS signal should be in the high state before the RESET signal is deasserted.
21.7 Command Sequence for Read/Write Operations for Page Size 256 Bytes (Except Status
Register Read, Manufacturer and Device ID Read)
SI (INPUT)
CMD
8 bits
8 bits
8 bits
X X X X X X X X X X X X X X X
X X X X X X X X
LSB
MSB
4 Don’t Care
Bits
Page Address
(A19 - A8)
Byte/Buffer Address
(A7 - A0/BFA7 - BFA0)
21.8 Command Sequence for Read/Write Operations for Page Size 264 Bytes (Except Status
Register Read, Manufacturer and Device ID Read)
SI (INPUT)
CMD
8 bits
8 bits
8 bits
X X X X X X X X X X X X X X X
X
X X X X X X X X
LSB
MSB
3 Don’t Care
Bits
Page Address
(PA11 - PA0)
Byte/Buffer Address
(BA8 - BA0/BFA8 - BFA0)
38
AT45DB081D
3596E–DFLASH–02/07
ATMEL [ ATMEL ]
