AT26DF321 [Preliminary]
Figure 2-1.
CS
SO
WP
GND
8-SOIC Top View
1
2
3
4
8
7
6
5
VCC
NC
SCK
SI
Figure 2-2.
16-SOIC Top View
NC
VCC
NC
NC
NC
NC
CS
SO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SCK
SI
NC
NC
NC
NC
GND
WP
3. Block Diagram
CS
CONTROL AND
PROTECTION LOGIC
I/O BUFFERS
AND LATCHES
SCK
SI
SO
SRAM
DATA BUFFER
INTERFACE
CONTROL
AND
LOGIC
ADDRESS LATCH
Y-DECODER
Y-GATING
WP
X-DECODER
FLASH
MEMORY
ARRAY
4. Memory Array
To provide the greatest flexibility, the memory array of the AT26DF321 can be erased in four lev-
els of granularity including a full chip erase. In addition, the array has been divided into physical
sectors of uniform size, of which each sector can be individually protected from program and
erase operations. The size of the physical sectors is optimized for both code and data storage
applications, allowing both code and data segments to reside in their own isolated
regions.
illustrates the breakdown of each erase level as well as the break-
down of each physical sector.
3
3633C–DFLASH–08/06
ATMEL [ ATMEL CORPORATION ]
