AT24C128/256
Pin Description
SERIAL CLOCK (SCL):
The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA):
The SDA pin is bidirectional for serial data transfer. This pin is open-
drain driven and may be wire-ORed with any number of other open-drain or open collector
devices.
DEVICE/ADDRESSES (A1, A0):
The A1 and A0 pins are device address inputs that are hard-
wired or left not connected for hardware compatibility with other AT24CXX devices. When the
pins are hardwired, as many as four 128K/256K devices may be addressed on a single bus
system (device addressing is discussed in detail under the Device Addressing section). If the
pins are left floating, the A1 and A0 pins will be internally pulled down to GND if the capacitive
coupling to the circuit board V
CC
plane is <3 pF. If coupling is >3 pF, Atmel recommends con-
necting the address pins to GND.
WRITE PROTECT (WP):
The write protect input, when connected to GND, allows normal write
operations. When WP is connected high to V
CC
, all write operations to the memory are inhib-
ited. If the pin is left floating, the WP pin will be internally pulled down to GND if the capacitive
coupling to the circuit board V
CC
plane is <3 pF. If coupling is >3 pF, Atmel recommends con-
necting the pin to GND.
Memory
Organization
AT24C128/256, 128K/256K SERIAL EEPROM:
The 128K/256K is internally organized as
256/512 pages of 64-bytes each. Random word addressing requires a 14/15-bit data word
address.
3
0670T–SEEPR–3/07
ATMEL [ ATMEL CORPORATION ]
