AT24C128/256
Pin Description
SERIAL CLOCK (SCL):
The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA):
The SDA pin is bidirectional for serial data transfer. This pin is open-
drain driven and may be wire-ORed with any number of other open-drain or open collector
devices.
DEVICE/PAGE ADDRESSES (A1, A0):
The A1 and A0 pins are device address inputs that
are hardwired or left not connected for hardware compatibility with AT24C32/64. When the
pins are hardwired, as many as four 128K/256K devices may be addressed on a single bus
system (device addressing is discussed in detail under the Device Addressing section). When
the pins are not hardwired, the default A
1
and A
0
are zero.
WRITE PROTECT (WP):
The write protect input, when tied to GND, allows normal write oper-
ations. When WP is tied high to V
CC
, all write operations to the memory are inhibited. If left
unconnected, WP is internally pulled down to GND. Switching WP to V
CC
prior to a write oper-
ation creates a software write protect function.
Memory
Organization
AT24C128/256, 128K/256K SERIAL EEPROM:
The 128K/256K is internally organized as
256/512 pages of 64-bytes each. Random word addressing requires a 14/15-bit data word
address.
3
0670K–SEEPR–7/03
ATMEL [ ATMEL CORPORATION ]
