AT24C02BN-SH-T 参数 Datasheet PDF下载

AT24C02B

4. Bus Timing

Figure 4-1.

SCL: Serial Clock, SDA: Serial Data I/O

®

t

F

t

HIGH

t

LOW

t

R

SCL

t

SU.STA

t

HD.STA

t

LOW

t

HD.DAT

t

SU.DAT

t

SU.STO

SDA IN

t

AA

t

DH

t

BUF

SDA OUT

5. Write Cycle Timing

Figure 5-1.

SCL: Serial Clock, SDA: Serial Data I/O

SCL

SDA

8th BIT

ACK

WORDn

t

wr

STOP

CONDITION

Note:

(1)

START

CONDITION

1. The write cycle time t

WR

is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

7

5126H–SEEPR–8/07