14 JTAG and Nexus debug ports
14.1 JTAG port interface
Figure 14-1. JTAG port interface example schematic.
TMS
TDO
2 x 5
header
1
3
5
7
9
2
4
TCK
TDO
TMS
EVTO
TDI
GND
VCC
VDD
100 nF
TCK
6
RESET
RESET
8
10
GND
TDI
Table 14-1. JTAG port interface checklist.
Signal name Recommended pin connection
Description
TMS
TDO
TCK
Test mode select, sampled on rising TCK
Test data output, driven on falling TCK
Test clock, fully asynchronous to system clock frequency
Device external reset line
RESET
TDI
Test data input, sampled on rising TCK
Event output, not used
EVTO
14.2 Nexus port interface
Do not use any capacitors on NEXUS lines because they can cause a speed
limitation. NEXUS uses GPIO multiplexed lines, and these should be dedicated for
NEXUS when used.
24
AVR32768
32157A-AVR-12/10
ATMEL [ ATMEL ]
