AD7322
TIMING SPECIFICATIONS
Preliminary Technical Data
Table 2. Unless otherwise noted,
V
DD
= +4.75V to + 16.5V, V
SS
= -4.75 to –16.5V, V
CC
=2.7V to 5.25, V
DRIVE
=2.7V to 5.25, V
REF
=
2.5V Internal/External, T
A
= T
MAX
to T
MIN
Parameter
f
SCLK
t
CONVERT
t
QUIET
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
Limit at T
MIN
, T
MAX
10
20
16×t
SCLK
50
10
10
20
TBD
0.4t
SCLK
0.4t
SCLK
10
25
10
TBD
5
1
TBD
Unit
kHz min
MHz max
ns max
ns max
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns min
µs max
µs max
Description
T
SCLK
= 1/f
SCLK
Minimum Time between End of Serial Read and Next Falling Edge of CS
Minimum CS Pulse width
CS to SCLK Setup Time
Delay from CS until D
OUT
Three-State Disabled
Data Access Time after SCLK Falling Edge.
SCLK Low Pulsewidth
SCLK High Pulsewidth
SCLK to Data Valid Hold Time
SCLK Falling Edge to D
OUT
High Impedance
SCLK Falling Edge to D
OUT
High Impedance
DIN set-up time prior to SCLK falling edge
DIN hold time after SCLK falling edge
Power up from Auto Standby
Power up from Full Shutdown/Auto Shutdown Mode
Figure 2. Serial Interface timing Diagram
Rev. PrE | Page 5 of 18
ATMEL [ ATMEL CORPORATION ]
