L67132/L67142
Timing Waveform of Write Cycle no 1, R/W Controlled Timing (32, 33, 34, 38)
Timing Waveform of Write Cycle no 2, CS Controlled Timing (32, 33, 34, 36)
Notes : 32. R/W must be high during all address transitions.
33. A write occurs during the overlap (t or t ) of a low CS and a low R/W.
SW
WP
34.
t
is measured from the earlier of CS or R/W going high to the end of write cycle.
WR
35. During this period, the I/O pins are in the output state, and input signals must not be applied.
36. If the CS low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the high
impedance state.
37. Transition is measured ± 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled
and not 100 % tested.
38. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of t or (t
+ t
DW
)
WP
WZ
to allow the I/O drivers to turn off and data to be placed on the bus for the required t . If OE is high during an R/W
DW
controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
39. To access RAM, CS = VIL.
.
WP
MATRA MHS
Rev. D (19 Fev. 97)
9
ATMEL [ ATMEL ]
