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90USB82-16MU 参数 Datasheet PDF下载

90USB82-16MU图片预览
型号: 90USB82-16MU
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器具有ISP功能的Flash 8 / 16K字节 [8-bit Microcontroller with 8/16K Bytes of ISP Flash]
分类和应用: 微控制器和处理器外围集成电路异步传输模式ATM时钟
文件页数/大小: 306 页 / 2299 K
品牌: ATMEL [ ATMEL ]
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AT90USB82/162  
Note:  
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O  
SLEEP, and PUD are common to all ports. All other signals are unique for each pin.  
,
Table 11-2 summarizes the function of the overriding signals. The pin and port indexes from Fig-  
ure 11-5 are not shown in the succeeding tables. The overriding signals are generated internally  
in the modules having the alternate function.  
Table 11-2. Generic Description of Overriding Signals for Alternate Functions  
Signal Name  
Full Name  
Description  
If this signal is set, the pull-up enable is controlled by the PUOV  
signal. If this signal is cleared, the pull-up is enabled when  
{DDxn, PORTxn, PUD} = 0b010.  
Pull-up Override  
Enable  
PUOE  
If PUOE is set, the pull-up is enabled/disabled when PUOV is  
set/cleared, regardless of the setting of the DDxn, PORTxn,  
and PUD Register bits.  
Pull-up Override  
Value  
PUOV  
DDOE  
DDOV  
If this signal is set, the Output Driver Enable is controlled by the  
DDOV signal. If this signal is cleared, the Output driver is  
enabled by the DDxn Register bit.  
Data Direction  
Override Enable  
If DDOE is set, the Output Driver is enabled/disabled when  
DDOV is set/cleared, regardless of the setting of the DDxn  
Register bit.  
Data Direction  
Override Value  
If this signal is set and the Output Driver is enabled, the port  
value is controlled by the PVOV signal. If PVOE is cleared, and  
the Output Driver is enabled, the port Value is controlled by the  
PORTxn Register bit.  
Port Value  
Override Enable  
PVOE  
Port Value  
Override Value  
If PVOE is set, the port value is set to PVOV, regardless of the  
setting of the PORTxn Register bit.  
PVOV  
PTOE  
Port Toggle  
Override Enable  
If PTOE is set, the PORTxn Register bit is inverted.  
Digital Input  
Enable Override  
Enable  
If this bit is set, the Digital Input Enable is controlled by the  
DIEOV signal. If this signal is cleared, the Digital Input Enable  
is determined by MCU state (Normal mode, sleep mode).  
DIEOE  
DIEOV  
Digital Input  
Enable Override  
Value  
If DIEOE is set, the Digital Input is enabled/disabled when  
DIEOV is set/cleared, regardless of the MCU state (Normal  
mode, sleep mode).  
This is the Digital Input to alternate functions. In the figure, the  
signal is connected to the output of the schmitt trigger but  
before the synchronizer. Unless the Digital Input is used as a  
clock source, the module with the alternate function will use its  
own synchronizer.  
DI  
Digital Input  
This is the Analog Input/output to/from alternate functions. The  
signal is connected directly to the pad, and can be used bi-  
directionally.  
Analog  
Input/Output  
AIO  
The following subsections shortly describe the alternate functions for each port, and relate the  
overriding signals to the alternate function. Refer to the alternate function description for further  
details.  
11.3.1  
MCU Control Register – MCUCR  
Bit  
7
6
5
4
3
2
1
0
JTD  
PUD  
IVSEL  
IVCE  
MCUCR  
73  
7707D–AVR–07/08  
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