The 32 general purpose working registers, 64 I/O registers, and the 512 bytes of internal data
SRAM in the AT90USB82/162 are all accessible through all these addressing modes. The Reg-
ister File is described in “General Purpose Register File” on page 11.
Figure 5-2. Data Memory Map
Data Memory
$0000
$0020
$0060
$0100
-
-
-
$001
$005
$00FF
F
F
32
64 I/O
160
R
eg
eg
xt I/O
i
st
e
r
s
e
R
R
i
st
r
s
eg.
E
In
t
(
e
r
na
512
l
S
x
R
8)
A
M
$2FF
5.2.1
Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clkCPU cycles as described in Figure 5-3.
Figure 5-3. On-chip Data SRAM Access Cycles
T1
T2
T3
clkCPU
Address valid
Compute Address
Address
Data
WR
Data
RD
Memory Access Instruction
Next Instruction
5.3
EEPROM Data Memory
The AT90USB82/162 contains 512 bytes of data EEPROM memory. It is organized as a sepa-
rate data space, in which single bytes can be read and written. The EEPROM has an endurance
of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is
described in the following, specifying the EEPROM Address Registers, the EEPROM Data Reg-
ister, and the EEPROM Control Register.
18
AT90USB82/162
7707D–AVR–07/08
ATMEL [ ATMEL ]
