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90USB82-16MU 参数 Datasheet PDF下载

90USB82-16MU图片预览
型号: 90USB82-16MU
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器具有ISP功能的Flash 8 / 16K字节 [8-bit Microcontroller with 8/16K Bytes of ISP Flash]
分类和应用: 微控制器和处理器外围集成电路异步传输模式ATM时钟
文件页数/大小: 306 页 / 2299 K
品牌: ATMEL [ ATMEL ]
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Receiver will generate a parity value for the incoming data and compare it to the UPMn setting.  
If a mismatch is detected, the UPEn Flag in UCSRnA will be set.  
Table 17-5. UPMn Bits Settings  
UPMn1  
UPMn0  
Parity Mode  
0
0
1
1
0
1
0
1
Disabled  
Reserved  
Enabled, Even Parity  
Enabled, Odd Parity  
• Bit 3 – USBSn: Stop Bit Select  
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores  
this setting.  
Table 17-6. USBS Bit Settings  
USBSn  
Stop Bit(s)  
1-bit  
0
1
2-bit  
• Bit 2:1 – UCSZn1:0: Character Size  
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits  
(Character SiZe) in a frame the Receiver and Transmitter use.  
Table 17-7. UCSZn Bits Settings  
UCSZn2  
UCSZn1  
UCSZn0  
Character Size  
5-bit  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
6-bit  
7-bit  
8-bit  
Reserved  
Reserved  
Reserved  
9-bit  
• Bit 0 – UCPOLn: Clock Polarity  
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is  
used. The UCPOLn bit sets the relationship between data output change and data input sample,  
and the synchronous clock (XCKn).  
Table 17-8. UCPOLn Bit Settings  
UCPOLn  
Transmitted Data Changed (Output of TxDn Pin)  
Received Data Sampled (Input on RxDn Pin)  
Falling XCKn Edge  
0
1
Rising XCKn Edge  
Falling XCKn Edge  
Rising XCKn Edge  
168  
AT90USB82/162  
7707D–AVR–07/08  
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