AT90USB64/128
Figure 8-1. Reset Logic
DATA BUS
MCU Status
Register (MCUSR)
Power-on Reset
Circuit
Brown-out
Reset Circuit
BODLEVEL [2..0]
Pull-up Resistor
SPIKE
FILTER
JTAG Reset
Register
Watchdog
Oscillator
Delay Counters
Clock
CK
Generator
TIMEOUT
CKSEL[3:0]
SUT[1:0]
Table 8-1.
Symbol Parameter
Power-on Reset Threshold
Reset Characteristics(1)
Condition
Min
Typ
Max Units
TBD TBD TBD
V
Voltage (rising)
VPOT
Power-on Reset Threshold
Voltage (falling)(2)
TBD TBD TBD
TBD TBD TBD
TBD TBD TBD
V
V
VRST
tRST
RESET Pin Threshold Voltage
Minimum pulse width on RESET
Pin
ns
Notes: 1. Values are guidelines only. Actual values are TBD.
2. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling)
8.0.3
Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in Table 8-1. The POR is activated whenever VCC is below the detection level. The
POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply
voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after VCC rise. The RESET signal is activated again, without any delay,
when VCC decreases below the detection level.
59
7593A–AVR–02/06
ATMEL [ ATMEL ]
