AT90USB64/128
AT90USB64/128 achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
2.1
Block Diagram
Block Diagram
Figure 2-1.
PF7 - PF0
PA7 - PA0
PC7 - PC0
VCC
GND
PORTF DRIVERS
PORTA DRIVERS
PORTC DRIVERS
DATA REGISTER
PORTF
DATA DIR.
REG. PORTF
DATA REGISTER
PORTA
DATA DIR.
REG. PORTA
DATA REGISTER
PORTC
DATA DIR.
REG. PORTC
8-BIT DATA BUS
AVCC
AGND
AREF
JTAG TAP
PROGRAM
COUNTER
ADC
POR - BOD
RESET
INTERNAL
OSCILLATOR
CALIB. OSC
STACK
POINTER
WATCHDOG
TIMER
OSCILLATOR
OSCILLATOR
ON-CHIP DEBUG
PROGRAM
FLASH
SRAM
MCU CONTROL
REGISTER
TIMING AND
CONTROL
BOUNDARY-
SCAN
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTERS
X
Y
Z
TIMER/
COUNTERS
PROGRAMMING
LOGIC
INSTRUCTION
DECODER
INTERRUPT
UNIT
CONTROL
LINES
ALU
EEPROM
PLL
STATUS
REGISTER
USART0
SPI
USB
TWO-WIRE SERIAL
INTERFACE
ANALOG
COMPARATOR
DATA REGISTER
PORTE
DATA DIR.
REG. PORTE
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
DATA REGISTER
PORTD
DATA DIR.
REG. PORTD
+
-
DATA REG.
PORTG
DATA DIR.
REG. PORTG
PORTE DRIVERS
PORTB DRIVERS
PORTD DRIVERS
PORTG DRIVERS
PE7 - PE0
PB7 - PB0
PD7 - PD0
PG4 - PG0
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
RESET
XTAL1
XTAL2
5
7593A–AVR–02/06
ATMEL [ ATMEL CORPORATION ]
