AT90USB64/128
23.13 OUT Pipe management ...................................................................................297
23.14 IN Pipe management .......................................................................................298
23.15 Interrupt system ...............................................................................................299
23.16 Registers ..........................................................................................................300
24 Analog Comparator ............................................................................. 313
24.1 Analog Comparator Multiplexed Input ..............................................................315
25 Analog to Digital Converter - ADC ..................................................... 316
25.1 Features ...........................................................................................................316
25.2 Operation .........................................................................................................317
25.3 Starting a Conversion ......................................................................................318
25.4 Prescaling and Conversion Timing ..................................................................319
25.5 Changing Channel or Reference Selection ......................................................322
25.6 ADC Noise Canceler ........................................................................................323
25.7 ADC Conversion Result ...................................................................................327
25.8 ADC Register Description ................................................................................329
26 JTAG Interface and On-chip Debug System ..................................... 335
26.1 Overview ..........................................................................................................335
26.2 Test Access Port – TAP ...................................................................................335
26.3 TAP Controller .................................................................................................337
26.4 Using the Boundary-scan Chain ......................................................................338
26.5 Using the On-chip Debug System ....................................................................338
26.6 On-chip Debug Specific JTAG Instructions ......................................................339
26.7 On-chip Debug Related Register in I/O Memory .............................................340
26.8 Using the JTAG Programming Capabilities .....................................................340
26.9 Bibliography .....................................................................................................340
27 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 341
27.1 Features ...........................................................................................................341
27.2 System Overview .............................................................................................341
27.3 Data Registers .................................................................................................341
27.4 Boundary-scan Specific JTAG Instructions ......................................................343
27.5 Boundary-scan Related Register in I/O Memory .............................................344
27.6 Boundary-scan Chain ......................................................................................345
27.7 AT90USB64/128 Boundary-scan Order ...........................................................348
27.8 Boundary-scan Description Language Files ....................................................351
6
7593A–AVR–02/06
ATMEL [ ATMEL ]
