AT90USB64/128
6.1.4
6.1.5
6.1.6
Asynchronous Timer Clock – clkASY
The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly
from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows
using this Timer/Counter as a real-time counter even when the device is in sleep mode.
ADC Clock – clkADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
USB Clock – clkUSB
The USB is provided with a dedicated clock domain. This clock is generated with an on-chip PLL
running at 48MHz. The PLL always multiply its input frequency by 24. Thus the PLL clock regis-
ter should be programmed by software to generate a 2MHz clock on the PLL input.
6.2
Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits as shown
below. The clock from the selected source is input to the AVR clock generator, and routed to the
appropriate modules.
Table 6-1.
Device Clocking Options Select(1)
Device Clocking Option
Low Power Crystal Oscillator
Reserved
CKSEL3..0
1111 - 1000
0111 - 0110
0101 - 0100
0011
Low Frequency Crystal Oscillator
Internal 128 kHz RC Oscillator
Calibrated Internal RC Oscillator
External Clock
0010
0000
Reserved
0001
Note:
1. For all fuses “1” means unprogrammed while “0” means programmed.
6.2.1
6.2.2
Default Clock Source
The device is shipped with internal RC oscillator at 8.0MHz and with the fuse CKDIV8 pro-
grammed, resulting in 1.0MHz system clock. The startup time is set to maximum and time-out
period enabled. (CKSEL = "0010", SUT = "10", CKDIV8 = "0"). The default setting ensures that
all users can make their desired clock source setting using any available programming interface.
Clock Startup Sequence
Any clock source needs a sufficient VCC to start oscillating and a minimum number of oscillating
cycles before it can be considered stable.
To ensure sufficient VCC, the device issues an internal reset with a time-out delay (tTOUT) after
the device reset is released by all other reset sources. “On-chip Debug System” on page 57
describes the start conditions for the internal reset. The delay (tTOUT) is timed from the Watchdog
Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The
selectable delays are shown in Table 6-2. The frequency of the Watchdog Oscillator is voltage
39
7593A–AVR–02/06
ATMEL [ ATMEL ]
