• 7-0 - PDAT7:0 - Pipe Data Bits
Set by the software to read/write a byte from/to the Pipe FIFO selected by PNUM.
Bit
7
6
5
4
3
2
1
0
-
-
-
-
-
PBYCT10 PBYCT9
PBYCT8
UPBCHX
Read/Write
Initial Value
R
0
R
0
R
0
0
0
0
0
0
• 7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 2-0 - PBYCT10:8 - Byte count (high) Bits
Set by hardware. This field is the MSB of the byte count of the FIFO endpoint. The LSB part is
provided by the UPBCLX register.
Bit
7
6
5
4
3
2
1
0
PBYCT7
PBYCT6
PBYCT5
PBYCT4
PBYCT3
PBYCT2
PBYCT1
PBYCT0 UPBCLX
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
• 7-0 - PBYCT7:0 - Byte Count (low) Bits
Set by the hardware. PBYCT10:0 is:
- (for OUT Pipe) increased after each writing into the Pipe and decremented after each byte
sent,
- (for IN Pipe) increased after each byte received by the host, and decremented after each byte
read by the software.
Bit
7
6
5
4
3
2
1
0
-
PINT6
PINT5
PINT4
PINT3
PINT2
PINT1
PINT0
UPINT
Read/Write
Initial Value
0
0
0
0
0
0
0
0
• 7 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 6-0 - PINT6:0 - Pipe Interrupts Bits
Set by hardware when an interrupt is triggered by the UPINTX register and if the corresponding
endpoint interrupt enable bit is set.
Cleared by hardware when the interrupt source is served.
312
AT90USB64/128
7593A–AVR–02/06
ATMEL [ ATMEL ]
