AT90USB64/128
Set by hardware when a new USB message is stored in the current bank of the Pipe. This trig-
gers an interrupt if the RXINE bit is set in the UPIENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
Bit
7
6
5
4
PERRE
RW
3
TXSTPE
RW
2
1
0
RXINE
RW
0
FLERRE NAKEDE
-
TXOUTE RXSTALLE
UPIENX
Read/Write
Initial Value
RW
0
RW
0
RW
0
RW
0
0
0
0
• 7 - FLERRE - Flow Error Interrupt enable
Set to enable the OVERFI and UNDERFI interrupts.
Clear to disable the OVERFI and UNDERFI interrupts.
• 6 - NAKEDE -NAK Handshake Received Interrupt Enable
Set to enable the NAKEDI interrupt.
Clear to disable the NAKEDI interrupt.
• 5 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 4 - PERRE -PIPE Error Interrupt Enable
Set to enable the PERRI interrupt.
Clear to disable the PERRI interrupt.
• 3 - TXSTPE - SETUP Bank ready Interrupt Enable
Set to enable the TXSTPI interrupt.
Clear to disable the TXSTPI interrupt.
• 2 - TXOUTE - OUT Bank ready Interrupt Enable
Set to enable the TXOUTI interrupt.
Clear to disable the TXOUTI interrupt.
• 1 - RXSTALLE - STALL Received Interrupt Enable
Set to enable the RXSTALLI interrupt.
Clear to disable the RXSTALLI interrupt.
• 0 - RXINE - IN Data received Interrupt Enable
Set to enable the RXINI interrupt.
Clear to disable the RXINI interrupt.
Bit
7
PDAT7
RW
6
PDAT6
RW
5
PDAT5
RW
4
PDAT4
RW
3
PDAT3
RW
2
PDAT2
RW
1
PDAT1
RW
0
PDAT0
RW
UPDATX
Read/Write
Initial Value
0
0
0
0
0
0
0
0
311
7593A–AVR–02/06
ATMEL [ ATMEL ]
