Set by hardware when a transaction underflow occurs in the current isochronous or interrupt
Pipe. The Pipe can’t send the data flow required by the device. A ZLP will be sent instead. An
interrupt is triggered if the FLERRE bit is set.
Shall be cleared by software. Setting by software has no effect.
Note: the Host controller has to send a OUT packet, but the bank is empty. A ZLP will be sent
and the UNDERFI bit is set
underflow for interrupt Pipe:
• 4 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 3-2 - DTSEQ1:0 - Toggle Sequencing Flag
Set by hardware to indicate the PID data of the current bank:
00b Data0
01b Data1
1xb Reserved.
For OUT Pipe, this value indicates the next data toggle that will be sent. This is not relative to the
current bank.
For IN Pipe, this value indicates the last data toggle received on the current bank.
• 1-0 - NBUSYBK1:0 - Busy Bank Flag
Set by hardware to indicate the number of busy bank.
For OUT Pipe, it indicates the number of busy bank(s), filled by the user, ready for OUT transfer.
For IN Pipe, it indicates the number of busy bank(s) filled by IN transaction from the Device.
00b All banks are free
01b 1 busy bank
10b 2 busy banks
11b Reserved.
Bit
7
INRQ7
RW
0
6
INRQ6
RW
0
5
INRQ5
RW
0
4
INRQ4
RW
0
3
INRQ3
RW
0
2
INRQ2
RW
0
1
INRQ1
RW
0
0
INRQ0
RW
0
UPINRQX
Read/Write
Initial Value
• 7-0 - INRQ7:0 - IN Request Number Before Freeze
Enter the number of IN transactions before the USB controller freezes the pipe. The USB con-
troller will perform (INRQ+1) IN requests before to freeze the Pipe. This counter is automatically
decreased by 1 each time a IN request has been successfully performed.
Bit
7
6
5
4
CRC16
RW
3
TIMEOUT
RW
2
1
0
-
COUNTER1:0
PID
RW
0
DATAPID DATATGL UPERRX
Read/Write
Initial Value
RW
0
RW
0
RW
0
RW
0
0
0
0
308
AT90USB64/128
7593A–AVR–02/06
ATMEL [ ATMEL ]
