AT90USB64/128
Each time the current bank is full, the RXIN and the FIFOCON bits are set. This triggers an inter-
rupt if the RXINE bit is set. The firmware can acknowledge the USB interrupt by clearing the
RXIN bit. The Firmware read the data and clear the FIFOCON bit in order to free the current
bank. If the IN Pipe is composed of multiple banks, clearing the FIFOCON bit will switch to the
next bank. The RXIN and FIFOCON bits are then updated by hardware in accordance with the
status of the new bank.
Example with 1 IN data bank
DATA
(to bank 0)
DATA
(to bank 0)
IN
ACK
HW
IN
ACK
HW
RXIN
SW
SW
FIFOCON
SW
read data from CPU
BANK 0
read data from CPU
BANK 0
Example with 2 IN data banks
DATA
(to bank 0)
DATA
(to bank 1)
IN
ACK
HW
IN
ACK
HW
RXIN
SW
SW
FIFOCON
SW
read data from CPU
BANK 0
read data from CPU
BANK 1
23.14.1 CRC Error (isochronous only)
A CRC error can occur during IN stage if the USB controller detects a bad received packet. In
this situation, the STALLEDI/CRCERRI interrupt is triggered. This does not prevent the RXINI
interrupt from being triggered.
23.15 Interrupt system
299
7593A–AVR–02/06
ATMEL [ ATMEL ]
