欢迎访问ic37.com |
会员登录 免费注册
发布采购

89C51RC2-UL 参数 Datasheet PDF下载

89C51RC2-UL图片预览
型号: 89C51RC2-UL
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器,带有16K / 32K字节的闪存 [8-bit Microcontroller with 16K/ 32K Bytes Flash]
分类和应用: 闪存微控制器
文件页数/大小: 127 页 / 1478 K
品牌: ATMEL [ ATMEL ]
 浏览型号89C51RC2-UL的Datasheet PDF文件第74页浏览型号89C51RC2-UL的Datasheet PDF文件第75页浏览型号89C51RC2-UL的Datasheet PDF文件第76页浏览型号89C51RC2-UL的Datasheet PDF文件第77页浏览型号89C51RC2-UL的Datasheet PDF文件第79页浏览型号89C51RC2-UL的Datasheet PDF文件第80页浏览型号89C51RC2-UL的Datasheet PDF文件第81页浏览型号89C51RC2-UL的Datasheet PDF文件第82页  
Table 60. WDTPRG Register  
WDTPRG - Watchdog Timer Out Register (0A7h)  
7
-
6
-
5
-
4
-
3
-
2
1
0
S2  
S1  
S0  
Bit  
Bit  
Number  
Mnemonic Description  
7
6
5
4
3
2
1
0
-
-
Reserved  
-
The value read from this bit is undetermined. Do not try to set this bit.  
-
-
S2  
S1  
S0  
WDT Time-out Select Bit 2  
WDT Time-out Select Bit 1  
WDT Time-out Select Bit 0  
S2  
0
0
0
0
1
1
1
1
S1  
0
0
1
1
0
0
1
1
S0Selected Time-out  
0(214 - 1) machine cycles, 16. 3 ms @ FOSCA = 12 MHz  
1(215 - 1) machine cycles, 32.7 ms @ FOSCA = 12 MHz  
0 (216 - 1) machine cycles, 65. 5 ms @ FOSCA = 12 MHz  
1(217 - 1) machine cycles, 131 ms @ FOSCA = 12 MHz  
0(218 - 1) machine cycles, 262 ms @ FOSCA = 12 MHz  
1 (219 - 1) machine cycles, 542 ms @ FOSCA = 12 MHz  
0(220 - 1) machine cycles, 1.05 s @ FOSCA = 12 MHz  
1 (221 - 1) machine cycles, 2.09 s @ FOSCA = 12 MHz  
Reset Value = XXXX X000  
WDT During Power-down In Power-down mode the oscillator stops, which means the WDT also stops. While in  
Power-down mode the user does not need to service the WDT. There are two methods  
and Idle  
of exiting Power-down mode: by a hardware reset or via a level activated external inter-  
rupt which is enabled prior to entering Power-down mode. When Power-down is exited  
with hardware reset, servicing the WDT should occur as it normally should whenever the  
AT89C51RB2/RC2 is reset. Exiting Power-down with an interrupt is significantly differ-  
ent. The interrupt is held low long enough for the oscillator to stabilize. When the  
interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the  
device while the interrupt pin is held low, the WDT is not started until the interrupt is  
pulled high. It is suggested that the WDT be reset during the interrupt service routine.  
To ensure that the WDT does not overflow within a few states of exiting of power-down,  
it is better to reset the WDT just before entering power-down.  
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the  
AT89C51RB2/RC2 while in Idle mode, the user should always set up a timer that will  
periodically exit Idle, service the WDT, and re-enter Idle mode.  
78  
AT89C51RB2/RC2  
4180E–8051–10/06  
 复制成功!