AT89C51RB2/RC2
Registers
Table 19. AUXR Register
AUXR - Auxiliary Register (8Eh)
7
6
-
5
4
-
3
2
1
0
DPU
M0
XRS1
XRS0
EXTRAM
AO
Bit
Bit
Number
Mnemonic Description
Disable Weak Pull-up
7
6
DPU
-
Cleared to activate the permanent weak pull up when latch data is logical 1
Set to disactive the weak pull-up (reduce power consumption)
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Pulse Length
Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock
periods (default).
5
M0
Set to stretch MOVX control: the RD and the WR pulse length is 30 clock
periods.
Reserved
4
3
-
The value read from this bit is indeterminate. Do not set this bit.
XRS1
XRAM Size
XRS1 XRS0 XRAM size
0
0
1
1
0
1
0
1
256 Bytes (default)
512 Bytes
2
XRS0
768 Bytes
1024 Bytes
EXTRAM Bit
Cleared to access internal XRAM using movx @ Ri/ @ DPTR.
EXTRAM Set to access external memory.
Programmed by hardware after Power-up regarding Hardware Security Byte
1
0
(HSB), default setting, XRAM selected.
ALE Output Bit
Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if
X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC
instruction is used.
AO
Reset Value = XX0X 00’HSB. XRAM’0b (see Table 65)
Not bit addressable
25
4180E–8051–10/06
ATMEL [ ATMEL ]
