Oscillator
To optimize the power consumption and execution time needed for a specific task, an
internal, prescaler feature has been implemented between the oscillator and the CPU
and peripherals.
Registers
Table 13. CKRL Register
CKRL – Clock Reload Register (97h)
7
6
5
4
3
2
1
0
CKRL7
CKRL6
CKRL5
CKRL4
CKRL3
CKRL2
CKRL1
CKRL0
Bit Number
Mnemonic
CKRL
Description
Clock Reload Register
7:0
Prescaler value
Reset Value = 1111 1111b
Not bit addressable
Table 14. PCON Register
PCON – Power Control Register (87h)
7
6
5
4
3
2
1
0
SMOD1
SMOD0
-
POF
GF1
GF0
PD
IDL
Bit Number
Bit Mnemonic Description
Serial Port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
7
SMOD1
SMOD0
-
Serial Port Mode bit 0
Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
6
5
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Power-off Flag
Cleared to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can
also be set by software.
4
POF
General-purpose Flag
3
2
1
0
GF1
GF0
PD
Cleared by software for general-purpose usage.
Set by software for general-purpose usage.
General-purpose Flag
Cleared by software for general-purpose usage.
Set by software for general-purpose usage.
Power-down Mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
Idle Mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
IDL
Reset Value = 00X1 0000b Not bit addressable
14
AT89C51RB2/RC2
4180E–8051–10/06
ATMEL [ ATMEL ]
