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89C51RB2-UM 参数 Datasheet PDF下载

89C51RB2-UM图片预览
型号: 89C51RB2-UM
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器,带有16K / 32K字节的闪存 [8-bit Microcontroller with 16K/ 32K Bytes Flash]
分类和应用: 闪存微控制器
文件页数/大小: 127 页 / 1478 K
品牌: ATMEL [ ATMEL ]
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Table 66. Program Lock Bits  
Program Lock Bits  
Security  
Level  
LB0  
LB1  
LB2 Protection Description  
1
U
U
U
No program lock features enabled.  
MOVC instruction executed from external program memory is disabled  
from fetching code Bytes from internal memory, EA is sampled and  
latched on reset, and further parallel programming of the Flash is  
disabled. ISP and software programming with API are still allowed.  
2
P
U
U
Same as 2, also verify through parallel programming interface is  
disabled.  
3
4
X
X
P
X
U
P
Same as 3, also external execution is disabled. (Default)  
Note:  
U: unprogrammed or "one" level.  
P: programmed or "zero" level.  
X: don’t care  
WARNING: Security level ‘2’ and ‘3‘ should only be programmed after Flash and code  
verification.  
These security bits protect the code access through the parallel programming interface.  
They are set by default to level 4. The code access through the ISP is still possible and  
is controlled by the "software security bits" which are stored in the extra Flash memory  
accessed by the ISP firmware.  
To load a new application with the parallel programmer, a chip erase must first be done.  
This will set the HSB in its inactive state and will erase the Flash memory. The part ref-  
erence can always be read using Flash parallel programming modes.  
Default Values  
The default value of the HSB provides parts ready to be programmed with ISP:  
BLJB: Programmed force ISP operation.  
X2: Unprogrammed to force X1 mode (Standard Mode).  
XRAM: Unprogrammed to valid XRAM  
LB2-0: Security level four to protect the code from a parallel access with maximum  
security.  
Software Registers  
Several registers are used, in factory and by parallel programmers, to make copies of  
hardware registers contents. These values are used by Atmel ISP.  
These registers are in the "Extra Flash Memory" part of the Flash memory. This block is  
also called "XAF" or eXtra Array Flash. They are accessed in the following ways:  
Commands issued by the parallel memory programmer.  
Commands issued by the ISP software.  
Calls of API issued by the application software.  
Several software registers are described in Table 67.  
88  
AT89C51RB2/RC2  
4180E–8051–10/06  
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