AT89C51RB2/RC2
Table 1. Minimum Reset Capacitor Value for a 50 kΩ Pull-down Resistor(1)
VDD Rise Time
10 ms
Oscillator
Start-Up Time
1 ms
820 nF
2.7 µF
100 ms
12 µF
5 ms
1.2 µF
20 ms
3.9 µF
12 µF
Note:
These values assume VDD starts from 0V to the nominal value. If the time between 2
on/off sequences is too fast, the power-supply de-coupling capacitors may not be fully
discharged, leading to a bad reset sequence.
Warm Reset
To achieve a valid reset, the reset signal must be maintained for at least 2 machine
cycles (24 oscillator clock periods) while the oscillator is running. The number of clock
periods is mode independent (X2 or X1).
Watchdog Reset
As detailed in Section “Hardware Watchdog Timer”, page 77, the WDT generates a 96-
clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of
the application in case of external capacitor or power-supply supervisor circuit, a 1 kΩ
resistor must be added as shown Figure 33.
Figure 33. Reset Circuitry for WDT Reset-out Usage
VDD
VDD
From WDT
+
Reset Source
P
RST
To CPU Core
and Peripherals
VDD
1K
RST
VSS
To Other
On-board
VSS
Circuitry
81
4180E–8051–10/06
ATMEL [ ATMEL ]
